Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of a semiconductor memory array of the floating gate memory cell type.
In the split-gate architecture, the memory cells can be formed in mirrored pairs. FIG. 1A illustrates a partially formed pair of memory cells, with floating gates 1 disposed over a substrate 2. A source region 3 is formed in the substrate 2, and is electrically connected to a source line 4. Layers of insulating materials 5 insulate floating gate 1, substrate 2, source regions 3 and source line 4 from each other. Control gates are formed by first forming a layer 6 of conductive material (such as polysilicon) over the structure, as shown in FIG. 1A. An anisotropic poly etch is then performed to remove layer 5 except for spacer portions that form the control gates, as illustrated in FIG. 1B. The problem with this configuration is that the control gate spacers 6 have sloped side wall profiles 7 that are difficult to insulate so the remaining features of the memory cells (such as drain region and electrical contacts connected thereto) can be formed. As illustrated in FIG. 1C, insulation spacers 8 can be formed against part of the sloped sidewall portion, but most of the sloped side wall portions of control gates 6 are still exposed.